C_CAPLIN

	C_CAPLIN Coplanar Metal-Insulator-Metal Capacitor to Ground Parameters Notes Equivalent Circuit
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Coplanar Metal-Insulator-Metal (MIM) Capacitor to Ground

The C_CAPLIN module represents a metal-insulator-metal capacitor (MIM-Capacitor) between the inner line and the ground planes of a coplanar line. The width of capacitor and its distance to the ground are given in a line type addressed by C_LTYPC. The total length of the capacitor is given by L. The dimensions of connected lines at ports are defined using data items addressed by C_ LTYP1 and C_LTYP2.

Parameters

Parameter	Description	Range of Usage
L	Total length of the capacitor
C_LTYPC	ID of coplanar transmission line applied at capacitive section
C_LTYP1	ID of coplanar transmission line applied at ports 1
C_LTYP2	ID of coplanar transmission line applied at ports 2
DIE_IDX	Index to dielectric layer definition for capacitors in currently selected foundry
C_SUB	ID of coplanar substrate definition
C_GRID	ID of simulation control data
TEMP	ID of element temperature definition used for noise computation

Notes

Presently, the C_CAPLIN module is not able to calculate the steps which are made if different line types are used for C_LTYP1, C_LTYP1 and C_LTYPC. Therefore, if a step configuration is used for layout reasons, the effect of such discontinuities are not taken into account during the simulation.
L is the total length of the capaciotr. Note that the effective length of the capacitive section is given by L- 2.cap_l. Therefor L has to be greater than 2.cap_l.
The connected lines addressed by C_LTYP1 and C_LTYP2 must have the same CEN_MET. CEN_MET in C_LTYPC must differ from CEN_MET in C_LTYP1 and C_LTYP2.
The index DIE_IDX is used for the selection of the desired dielectric layer in selected foundry. In case of DEFAULT foundry, two different dielectric layers are available (DIE_IDX =0 is not allowed). If DIE_IDX=1, the parameter die_h1, die_er1, die_td1, cap_l1 and cap_os1 are used.
The oversize of lower metal plate is defined by the keyword cap_os in selected foundry.
If L1 in selected C_GRID is not set to –1 or –2 (auto sizing), the minimum values for L1 is:

L1_min= max( W1+2S1+2GW1, W2+2S2+2GW2, WC+2SC+2GWC)

Equivalent Circuit

For the modeling of the C_CAPLIN element, a distributive equivalent circuit is used. Since the traveling wave effects along the capacitor is taken into account, , there is no limitation due to the length L. The model parameter are derived from quasi-static FD-calculations. The DC and RF losses (represented by R´) due to the skin effect are calculated using the surface current distribution on the conductors. The dielectric loss of the dielectric material represented by G´ (see die_er in C_TECH) is also taken into account.