Topic Master Thesis (M.Sc.) - Sigma Delta ADC

These tasks await you:

Planning, design, construction and programming of a flexibly configurable evaluation board with FPGA programming for a decimation filter chain architecture for delta-sigma converters. Carrying out series of measurements with this evaluation board to characterise the ADC architecture (data interface LVDS 500 MHz).

• Familiarisation with the signal processing of continuous time multibit sigma delta ADCs
• Concept, design and construction of an evaluation board (PCB) with FPGA digital part
• Defining interfaces to existing IMST sigma-delta analogue part (55nm CMOS; chip-on-board)
• Adaptation of existing VHDL reference code (decimation filter) for FPGA implementation (design environment AMD-Xilinx Vivado)
• Carry out verification and FPGA implementation
• Functional verification using typical 4-bit reference data input currents (SNR) and configuration specifications (pattern generator)
• Measurement series in the measurement setup with the existing IMST Sigma Delta analogue chip

This is what we offer you:

• Career and further education opportunities
• Flexible working time models
• A variety of exciting tasks in an active team
• An attractive workplace with plenty of creative freedom
• Team events

This is what we expect from you:

• You are currently in an advanced degree program with specialization in electrical engineering or in a similar degree program
• Good German and English language skills
• Knowledge of digital circuits and systems
• FPGA design know-how
• You are a strong team player, have a passion for coordinating technical matters and are open-minded